The revised model of the HiFive1 embedded improvement board from SiFive provides Wi-Fi and Bluetooth assist on the Arduino-compatible board.
Amazon’s improvement of a homegrown Arm CPU, mixed with new AMD EPYC powered cases introduced this month, threaten Intel’s hegemony in cloud computing and enterprise servers.
On Tuesday, SiFive launched a modest improve to the HiFive1 single-board laptop (SBC), which is now powered by the newly-released FE310-G002 revision of SiFive’s E31 RISC-V core. The unique HiFive1 and FE310-G00zero had been launched in 2016.
The HiFive1 is 68 mm x 51 mm, 32-bit RISC-V improvement board, although it’s meant for Web of Issues (IoT), Arduino, and real-time embedded functions. This isn’t a board on which builders ought to count on to run a desktop or server Linux distribution, just like the Raspberry Pi three B+.
The FE310-G002 provides a low-power sleep mode and a three.3V always-on area (elevated from the 1.8V of the unique), in addition to a I²C, and a second UART. It comprises a 32-bit RV32IMAC core with 16 KB L1 instruction cache, 16 KB SRAM, and multiply/divide. The chip runs at “320+ MHz,” in accordance with SiFive, and is touted as “among the many quickest microcontrollers in the marketplace.”
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The HiFive1 Rev B provides a Segger J-Hyperlink debugger. With this, the HiFive1 seems as a mass storage system when hooked up to a PC, enabling drag-and-drop flash programming. With the addition of the ESP32 co-processor, the board contains Wi-Fi and Bluetooth capabilities.
SiFive gives a five-pack of the FE310-G002 chips for $25, a single HiFive1 Rev B for $49 when preordered, or a five-pack of the HiFive1 Rev B for $239 when preordered, all of which can be found through Crowd Provide. Orders are anticipated to ship on April 16, 2019.
RISC-V is an open-source instruction set structure (ISA) which requires no royalties to be paid when manufacturing RISC-V CPUs. The mission goals to design chips that may exchange Arm CPUs in a wide range of use circumstances. SiFive was based by the inventors of the RISC-V ISA. The initiative has the backing of the Linux Basis, with the newly-formed CHIPS Alliance seeing code and specification donations from Google, NVIDIA, Western Digital, and others.